? semiconductor components industries, llc, 2015 february, 2015 ? rev. 4 1 publication order number: esd8008/d esd8008 esd protection diode low capacitance array for high speed data lines the esd8008 is designed specifically to protect four high speed differential pairs. ultra ? low capacitance and low esd clamping voltage make this device an ideal solution for protecting voltage sensitive high speed data lines. the flow ? through style package allows for easy pcb layout and matched trace lengths necessary to maintain consistent impedance for the high speed lines. features ? integrated 4 pairs (8 lines) high speed data ? single connect, flow through routing ? low capacitance (0.35 pf max, i/o to gnd) ? protection for the following iec standards: iec 61000 ? 4 ? 2 level 4 (esd) 15 kv (contact) iec 61000 ? 4 ? 5 (lightning) 5 a (8/20 s) ? ul flammability rating of 94 v ? 0 ? sz prefix for automotive and other applications requiring unique site and control change requirements; aec ? q101 qualified and ppap capable ? these devices are pb ? free, halogen free/bfr free and are rohs compliant typical applications ? v ? by ? one hs ? lvds ? display port maximum ratings (t j = 25 c unless otherwise noted) rating symbol value unit operating junction temperature range t j ? 55 to +125 c storage temperature range t stg ? 55 to +150 c lead solder temperature ? maximum (10 seconds) t l 260 c iec 61000 ? 4 ? 2 contact (esd) iec 61000 ? 4 ? 2 air (esd) esd esd 15 15 kv kv maximum peak pulse current 8/20 s @ t a = 25 c (i/o ? gnd) i pp 5.0 a stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. see application note and8308/d for further description of survivability specs. marking diagram device package shipping ordering information udfn14 case 517cn www. onsemi.com esd8008mutag udfn14 (pb ? free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. 8008 = specific device code m = date code = pb ? free package 8008m 1 14 SZESD8008MUTAG udfn14 (pb ? free) 3000 / tape & reel
esd8008 www. onsemi.com 2 i/o figure 1. pin schematic figure 2. pin configuration note: only minimum of one pin needs to be connected to ground for functionality of all pins. i/o pin 1 i/o pin 2 i/o pin 4 i/o pin 5 i/o pin 7 i/o pin 8 i/o pin 10 i/o pin 11 center pins, pin 3, 6, 9, 12, 13, 14 note: common gnd ? only minimum of 1 gnd connection required gnd gnd gnd i/o gnd i/o i/o gnd i/o i/o gnd i/o i/o = 1 2 3 4 5 6 7 8 9 10 11 14 13 12
esd8008 www. onsemi.com 3 electrical characteristics (t a = 25 c unless otherwise noted) symbol parameter v rwm working peak voltage i r maximum reverse leakage current @ v rwm v br breakdown voltage @ i t i t test current v hold holding reverse voltage i hold holding reverse current r dyn dynamic resistance i pp maximum peak pulse current v c clamping voltage @ i pp v c = v hold + (i pp * r dyn ) i v v c v rwm v hold v br r dyn v c i r i t i hold ? i pp r dyn i pp v c = v hold + (i pp * r dyn ) electrical characteristics (t a = 25 c unless otherwise specified) parameter symbol conditions min typ max unit reverse working voltage v rwm i/o pin to gnd 3.3 v breakdown voltage v br i t = 1 ma, i/o pin to gnd 5.5 7.0 8.5 v reverse leakage current i r v rwm = 3.3 v, i/o pin to gnd 0.5 a holding reverse voltage v hold i/o pin to gnd 1.19 v holding reverse current i hold i/o pin to gnd 25 ma clamping voltage (note 1) v c iec61000 ? 4 ? 2, 8 kv contact see figures 3 and 4 v clamping voltage v c i pp = 1 a, any i/o to gnd (8/20 s pulse) 1.5 v clamping voltage v c i pp = 5 a, any i/o to gnd (8/20 s pulse) 5.0 v clamping voltage tlp (note 2) see figures 7 through 10 v c i pp = 8 a i pp = ? 8 a iec 61000 ? 4 ? 2 level 2 equivalent ( 4 kv contact, 4 kv air) 4.6 ? 5.1 v i pp = 16 a i pp = ? 16 a iec 61000 ? 4 ? 2 level 4 equivalent ( 8 kv contact, 15 kv air) 8.1 ? 10.3 dynamic resistance r dyn i/o pin to gnd gnd to i/o pin 0.43 0.50 junction capacitance c j v r = 0 v, f = 1 mhz between i/o pins and gnd v r = 0 v, f = 2.5 ghz between i/o pins and gnd v r = 0 v, f = 5.0 ghz between i/o pins and gnd v r = 0 v, f = 1 mhz, between i/o pins 0.30 0.20 0.20 0.10 0.35 0.16 pf product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 1. for test procedure see figures 5 and 6 and application note and8307/d. 2. ansi/esd stm5.5.1 ? electrostatic discharge sensitivity testing using transmission line pulse (tlp) model. tlp conditions: z 0 = 50 , t p = 100 ns, t r = 4 ns, averaging window; t 1 = 30 ns to t 2 = 60 ns. 0 ? 10 ? 20 ? 30 ? 40 ? 50 ? 60 ? 70 ? 80 ? 90 ? 20 0 20 40 60 80 100 140 120 figure 3. iec61000 ? 4 ? 2 +8 kv contact esd clamping voltage figure 4. iec61000 ? 4 ? 2 ? 8 kv contact clamping voltage ? 20 0 20 40 60 80 100 140 120 90 time (ns) time (ns) voltage (v) voltage (v) 80 70 60 50 40 30 20 10 0 ? 10
esd8008 www. onsemi.com 4 iec 61000 ? 4 ? 2 spec. level test volt- age (kv) first peak current (a) current at 30 ns (a) current at 60 ns (a) 1 2 7.5 4 2 2 4 15 8 4 3 6 22.5 12 6 4 8 30 16 8 i peak 90% 10% iec61000 ? 4 ? 2 waveform 100% i @ 30 ns i @ 60 ns t p = 0.7 ns to 1 ns figure 5. iec61000 ? 4 ? 2 spec figure 6. diagram of esd clamping voltage test setup 50 50 cable tvs oscilloscope esd gun the following is taken from application note and8307/d ? characterization of esd clamping performance. esd voltage clamping for sensitive circuit elements it is important to limit the voltage that an ic will be exposed to during an esd event to as low a voltage as possible. the esd clamping voltage is the voltage drop across the esd protection diode during an esd event per the iec61000 ? 4 ? 2 waveform. since the iec61000 ? 4 ? 2 was written as a pass/fail spec for larger systems such as cell phones or laptop computers it is not clearly de fined in the spec how to specify a clamping voltage at the device level. on semiconductor has developed a way to examine the entire voltage waveform across the esd protection diode over the time domain of an esd pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all esd protection diodes. for more information on how on semiconductor creates these screenshots and how to interpret them please refer to and8307/d.
esd8008 www. onsemi.com 5 figure 7. positive tlp i ? v curve figure 8. negative tlp i ? v curve tlp current (a) v c , voltage (v) equivalent v iec (kv) 20 18 16 14 12 10 8 6 4 2 00 8 6 4 2 020 18 16 14 2468 12 10 tlp current (a) v c , voltage (v) equivalent v iec (kv) ? 20 0 8 6 4 2 020 18 16 14 2468 12 10 ? 18 ? 16 ? 14 ? 12 ? 10 ? 8 ? 6 ? 4 ? 2 0 note: tlp parameter: z 0 = 50 , t p = 100 ns, t r = 300 ps, averaging window: t 1 = 30 ns to t 2 = 60 ns. v iec is the equivalent voltage stress level calculated at the secondary peak of the iec 61000 ? 4 ? 2 waveform at t = 30 ns with 2 a/kv. see tlp description below for more information. v c = v hold + (i pp * r dyn ) 10 10 transmission line pulse (tlp) measurement transmission line pulse (tlp) provides current versus voltage (i ? v) curves in which each data point is obtained from a 100 ns long rectangular pulse from a charged transmission line. a simplified schematic of a typical tlp system is shown in figure 9. tlp i ? v curves of esd protection devices accurately demonstrate the product?s esd capability because the 10s of amps current levels and under 100 ns time scale match those of an esd event. this is illustrated in figure 10 where an 8 kv iec 61000 ? 4 ? 2 current waveform is compared with tlp current pulses at 8 a and 16 a. a tlp i ? v curve shows the voltage at which the device turns on as well as how well the device clamps voltage over a range of current levels. for more information on tlp measurements and how to interpret them please refer to and9007/d. figure 9. simplified schematic of a typical tlp system dut l s oscilloscope attenuator 10 m v c v m i m 50 coax cable 50 coax cable figure 10. comparison between 8 kv iec 61000 ? 4 ? 2 and 8 a and 16 a tlp waveforms
esd8008 www. onsemi.com 6 figure 11. iec61000 ? 4 ? 5 8/20 s pulse waveform time ( s) 50 0 ipp - peak pulse current - %ipp 100 t r = rise time to peak value [8 s] t f = decay time to half value [20 s] t r t f peak value half value 0 figure 12. clamping voltage vs. peak pulse current (t p = 8/20 s per figure 11) 8 7 6 5 4 3 2 1 0 08 7 6 5 1234 i pk (a) v pk (v) i/o ? gnd figure 13. junction capacitance; v r = 0, f = 500 mhz ? 10 ghz interface data rate (gbps) fundamental frequency (ghz) 3 rd harmonic frequency (ghz) esd8008 insertion loss ( ? db) v ? by ? one hs full hd (1920 x 1080p) 240 hz, 36bit color depth 3.71 1.854 (m1) 5.562 (m3) m1 = 0.146 m3 = 0.451 figure 14. esd8008 insertion loss
esd8008 www. onsemi.com 7 figure 15. v ? by ? one hs layout diagram (for lcd panel) esd8008 esd8008 rx0p rx0n rx1p rx1n rx2p rx2n rx3p rx3n rx4p rx4n rx5p rx5n rx6p rx6n rx7p rx7n tcon board connector timing controller pcb layout guidelines steps must be taken for proper placement and signal trace routing of the esd protection device in order to ensure the maximum esd survivability and signal integrity for the application. such steps are listed below. ? place the esd protection device as close as possible to the i/o connector to reduce the esd path to ground and improve the protection performance. ? make sure to use differential design methodology and impedance matching of all high speed signal traces. ? use curved traces when possible to avoid unwanted reflections. ? keep the trace lengths equal between the positive and negative lines of the differential data lanes to avoid common mode noise generation and impedance mismatch. ? place grounds between high speed pairs and keep as much distance between pairs as possible to reduce crosstalk.
esd8008 www. onsemi.com 8 latch-up considerations on semiconductor?s 8000 series of esd protection devices utilize a snap-back, scr type structure. by using this technology, the potential for a latch-up condition was taken into account by performing load line analyses of common high speed serial interfaces. example load lines for latch-up free applications and applications with the potential for latch-up are shown below with a generic iv characteristic of a snapback, scr type structured device overlaid on each. in the latch-up free load line case, the iv characteristic of the snapback protection device intersects the load-line in one unique point (v op , i op ). this is the only stable operating point of the circuit and the system is therefore latch-up free. in the non-latch up free load line case, the iv characteristic of the snapback protection device intersects the load-line in two points (v opa , i opa ) and (v opb , i opb ). therefore in this case, the potential for latch-up exists if the system settles at (v opb , i opb ) after a transient. because of this, esd8008 should not be used for hdmi applications ? esd8104 or esd8040 have been designed to be acceptable for hdmi applications without latch-up. please refer to application note and9116/d for a more in-depth explanation of latch-up considerations using esd8000 series devices. figure 16. example load lines for latch-up free applications and applications with the potential for latch-up i v v dd i ssmax i op v op i v v dd i ssmax i opa v opa i opb v opb esd8008 latch ? up free: v ? by ? one hs, displayport, lvds esd8008 potential latch ? up: hdmi 1.4/1.3a tmds table 1. summary of scr requirements for latch-up free applications application vbr (min) (v) ih (min) (ma) vh (min) (v) on semiconductor esd8000 series recommended pn hdmi 1.4/1.3a tmds 3.465 54.78 1.0 esd8104, esd8040 displayport 3.600 25.00 1.0 esd8004, esd8006, esd8008 v ? by ? one hs 1.980 21.70 1.0 esd8008 lvds 1.829 9.20 1.0 esd8008
esd8008 www. onsemi.com 9 package dimensions case 517cn issue o notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.10 and 0.20 mm from terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. dim min max millimeters a 0.45 0.55 a1 0.00 0.05 a3 0.13 ref b 0.15 0.25 d 5.50 bsc d2 0.45 0.55 e 1.50 bsc e 0.50 bsc l 0.20 0.40 0.10 c d e b a 2x 2x note 4 a a1 (a3) 0.10 c pin one reference 0.10 c 0.05 c c seating plane bottom view b 14x 0.10 b 0.05 a c c l side view top view note 3 1 11 14 12 3x *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* detail c l1 0.00 0.05 dimension: millimeters recommended l1 detail a l optional construction ?? 0.62 1.80 0.50 pitch package 0.26 14x e2 0.50 0.70 e m m e2 0.10 detail c 14x 0.50 detail a d2 ref 6x 0.43 outline 0.56 3x on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warrant y, representation or guarantee regarding the suitability of it s products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 esd8008/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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